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D$D$DFL$,hT$T$ |$ L$(lt$ D$D$ L$$$MkC0D$D$ D$ DF$)kC4D$D$ D$ DF$kC4Džp p x Džp @Džtu Džt Džxu Džx uҾ t Jf 拕p>苍tD$D$ DFT$$xL$ t$s<|$T$ D$ D$ $0jC<D$D$ D$ DF$ jC<u!u!DFL$T$ D$D$ $if> C@s@D$<D$ D$ DF$iC@ C@ C@ C@ C@f C@ @ C@@f {@ f CA CA Ff F F@F Ffj F F Ff F F& F fJ F@p CDKD|D$dD$ D$ DF$|hCDx! @u! u! u% D$ DF|$ t$L$T$D$D$ $h|@@ CHD$4D$ D$ DF$gCHExE! @EuE EuE EuE EuE EuE EuE EuE u @ u u! u!ET$ L$|$D$8Et$D$hD$ D$4ED$0ED$,ED$(ED$$ED$ ED$ DF$fCLD$xD$ D$ DF$^fU R CPD$D$ D$ DF$,fCP CTD$D$ D$ DF$eCXD$D$ D$ DF$eC\D$DD$ D$ DF$eC\ C\y C` D$D$ D$ DF$weC`D$D$ D$ DF$SeCdD$D$ D$ DF$/eCdD$D$ D$ DF$ eChD$ D$ D$ DF$dChD$D$ D$ DF$dClD$4D$ D$ DF$dClD$D$ D$ DF${dCpD$hD$ D$ DF$WdCpD$D$ D$ DF$3dCtD$D$ D$ DF$dCtD$D$ D$ DF$cCxD$D$ D$ DF$cCxD$D$ D$ DF$cDF$ D$dDFD$ D$ $D$ dDFD$ D$ $D$ dd D$D$ D$ DF$ c E% ঃduE!uuvD$E|$L$ D$8D$DFD$ $bFB F( F@t& f> UD$D$ D$ DF$Hb EfxE@EuE EuEEuEEuE@u uuuET$ |$t$D$,EL$D$D$ D$(ED$$ED$ ED$ DF$[aUW M D$HD$ D$ DF$ a D$|D$ D$ DF$` Љ% L$ L$D$D$ D$D$ ¡DFT$ $` D$D$ D$ DF$z` D$0D$ D$D$ DF$L` @ m 0 y f ; D$ D$ D$ DF$_ D$0D$ D$D$ DF$_ @l / x ; @ f E D$D$ D$ DF$^ uuuuDFT$ |$t$L$D$LD$ $}^U D$D$ D$ DF$D^ D$0D$ D$ DF$ ^ EuEEuEĵuvйZ uUD$DF|$L$ T$ UD$dD$ $T$] @Y > F F f D$D$ D$ DF$+] u!D$ DFD$*D$ $\ MD$D$ D$ DF$\ Em@uE EmuEmumumumuẺT$ |$t$D$ EЉL$D$0D$ D$ DF$$\Uf: F D$D$ D$ DF$[ D$LD$ D$ DF$[ D$D$ D$ DF$[ D$D$ D$ DF$z[ D$D$ D$ DF$R[ MD$D$ D$ DF$"[ E`uEإEiuEvu!uuu!E؉T$ |$t$D$ E܉L$D$D$ D$ DF$ZU < D$D$ D$ DF$HZ % Ƀu5 t& E`uEҿxЃ L$ MD$D$ DFt$ L$|$D$D$ $Y E䋃 D$|D$ D$ DF$Y EuE!E!xE X E!!u!uEL$M|$ t$D$$EL$T$ D$D$ DFD$ $XE @t%DFD$ D$ $DD$ YDF$ D$YDFD$ D$ $D$ YDFD$ D$ $D$ tY D$dD$ D$ DF$-X D$D$ D$ DF$X D$D$ D$ DF$W D$ D$ D$ DF$W 1[^_]Ív ELfDFD$ D$ $QD$ Xu HDžP!DžLC% uDžHfDžHE 놡DFD$ D$ $CD$ WDFD$ D$ $D$ W+t& DFD$ D$ $D$ sW DFD$ D$ $D$ CW DFD$ D$ $D$ W} DFD$ D$ $$D$ VD DFD$ D$ $D$ V DFD$ D$ $D$ V DFD$ D$ $eD$ SV DFD$ D$ $D$ #V DFD$ D$ $D$ U DFD$ D$ $D$ U^ DFD$ D$ $~D$ U! DFD$& D$ $D$ cU DFD$& D$ $D$ 3U DFD$$ D$ $|D$ Uj DFD$$ D$ $TD$ T- DFD$ D$ $eD$ T DFD$ D$ $ D$ sT] DFD$ D$ $LD$ CT DFD$ D$ $.D$ T DFD$) D$ $D$ S DFD$) D$ $D$ Si DFD$' D$ $D$ S, DFD$' D$ $XD$ SS DFD$ D$ $D$ #S DFD$ D$ $$D$ R DFD$ D$ ${D$ R& DFD$ D$ $D$ R DFD$ D$ $D$ cR DFD$ D$ $D$ 3R DFD$ D$ ${D$ R DFD$% D$ $D$ Q DFD$ D$ $D$ Qr DFD$' D$ $D$ sQC@DFD$ D$ $D$ CQC@ DFD$& D$ $D$ QC@@DFD$& D$ $8D$ P{@ wDFD$& D$ $`D$ PCAQDFD$& D$ $D$ PCA+DFD$# D$ $D$ SPFDFD$$ D$ $D$ #PFDFD$ D$ $D$ OF@DFD$ D$ $D$ OFDFD$ D$ $D$ OFqDFD$ D$ $ D$ cOFKDFD$ D$ $@D$ 3OF'DFD$ D$ $D$ OFDFD$ D$ $D$ NFDFD$ D$ $ D$ NF DFD$ D$ $:D$ sNF@DFD$ D$ $TD$ CNkDFD$ D$ $nD$ N@ DFD$' D$ $D$ MF DFD$% D$ $D$ M DFD$$ D$ $pD$ M DFD$" D$ $D$ SM DFD$ D$ $D$ #M] DFD$ D$ $xD$ L# , D$(( D$$$ D$ D$ D$ D$ D$ D$D$ D$ DF$[KDFD$$ D$ $ D$ QL5t& DFD$& D$ $D$ #LUWVS,E ]P @UD$1$ EC$D$J\$1D$>$ JD$K$ J& UZD$T$ D$Ju$ 0J@\$D$[$ iJUDZD$T$ D$IJ\t@ރtUDZD$T$ D$Jũ$ &J\u$ 1JEEd ÉEKt& |$D$f$ ID$T$ D$IE} t5tD$T$ D$pIu$ I$ qI} f u1ۋU UD D$D$q$ ID$T$ D$H;]t>߃tD$T$ D$Hu$ H;]u $ HUuBD$$ D$jHEXf] @b @ t& o @M + t& t& x $ v GFD$$ D$G^@' t& y @W t& 0 t& $ v 3GFD$$ D$F^f @h F $ @z t& T 2 t& $ sFF D$,$ D$7F^ f @J ( @~ \ t& 6 t& $ EFD$\$ D$E^f^ @O - f ` @> t& t& i $ DF D$$ D$DFPD$$ D$DFRD$$ D$zDFTD$ $ D$^DFVD$< $ D$BD D$h $ D$#D f=$&0 vQf=&& I f='&t& f=(& $ D $ Cf=!&t& f=#& f= $ $D D$y$ cC~D$n$ JC\D$d$ 1C:D$[$ CD$R$ BD$J$ BD$A$ BD$9$ BD$0$ BfD$($ BDD$ $ iB"D$$ PBD$$ 7BD$ $ BD$$ BD$$ A>D$$ A D$$ AD$$ AD$$ AD$$ oAD$$ VAiD$$ =AGD$$ $A&D$$ AD$$ @D$$ @D$$ @D$$ @BD$$ @ D$w$ u@D$o$ \@D$f$ C@D$^$ *@D$X$ @mD$O$ ?KD$H$ ?*D$B$ ?D$7$ ?D$-$ ?D$$$ {?D$$ b?D$$ I?"D$$ 0?D$$ ?D$$ >D$$ >D$$ >nD$$ >LD$$ >&D$$ >D$$ h>D$$ O>D$$ 6>oD$q$ >HD$$ >&D$$ =D$$ =D$$ =D$M$ =D$$ =xD$$ n=WD$s$ U=0D$$ <=D$$ #=D$$ =D$$ <D$|$ <$=D$ $ D$<D$/$ f T$ D$~< D$ $ D$_< D$ $ D$@<$ T<U D$ $ D$<E @> ۍv t& k I $ ;UBD$L$ D$;UB$D$x$ D$o;U D$$ D$M;E f tD$$ !;$ 5;UB.D$$ D$:UB0D$ $ D$:UB>D$,$ D$:UB@D$X$ D$:UBFD$$ D$z:,1[^_]D$$ \:D$}$ C:|D$v$ *:UD$m$ :3D$c$ 9D$Z$ 9D$S$ 9D$I$ 9$:$:v $:$:D$$ M9D$$ 49ED$$ 9D$$ 9D$$ 8$: UЉWVS\E+uEEuEEuEEuEEuE EuE@uҾxu@ufxE܉|$ t$\$D$4EL$T$ D$D$0ED$ D$,ED$(ED$$ED$ DF$u7\[^_]Ðt& UWVSE\} EGLEGLw % |t9EuE9CtE u9Ct7@FD$ D$ $D$ 8\[ [^_]ûE1E t& wՠE9uUvE DFL$ D$D$ $6FD$ FD$ FD$FD$FD$G D$D$ D$ DF$A6F D$FD$ D$ D$ DF$6} E} EE } } F D$FD$FD$FD$D$ D$ DF$5F,D$F(D$F$D$F D$D$ D$ DF$u5U U F0D$D$ D$ DF$?5 FD$FD$PD$ D$ DF$5F$D$F D$D$ D$ DF$4F,D$F(D$D$ D$ DF$4U UDF0D$D$ D$ DF$4^6\$F4D$ D$ D$ DF$V4te* 1z ?W G? D$ DF|$L$T$D$PD$ $3F7`u.u.uD$ DF|$\$L$D$|D$ $3} F<D$D D$ D$ DF$Y3F<F>D$ D$ D$ DF$+3F>FL% D$FHD$FDD$UD$ D$ D$ DF$2FRD$FQD$FPD$ D$ D$ DF$2}[ } FTD$D$ D$ DF$u2FXD$D$ D$ DF$P2FYD$(D$ D$ DF$+2} F\D$p D$ D$ DF$1F^D$D$ D$ DF$1F`D$4D$ % D$ DFT$$1FdD$D$ % D$ DFT$$s1FhD$ D$ % D$ DFT$$A1FlD$D$ % D$ DFT$$1FpD$ D$ % D$ DFT$$0FtD$x D$ D$ DF$0}vYF|D$FxD$D$ D$ DF$0}t( D$ D$ D$ DF$Y0} }* } D$( D$$ D$ D$ D$ D$ D$ D$D$ D$ DF$/ D$H D$D D$@ D$< D$8 D$4 D$0 D$, D$( D$$ D$ D$ D$ D$ D$ D$D$ D$ DF$ / D$( D$$ D$ D$ D$ D$ D$ D$(D$ D$ DF$.}vfEv-} t' D$D$ D$ DF$V.}t( D$<D$ D$ DF$(.} } }t}\1[^_]FXD$D$ D$ DF$-G?1^ DFD$xD$ \$ $i- @ v U " D$D$ ȃD$ D$ЃD$DFT$L$ $, D$ D$PD$ D$ DF$, D$D$ D$ DF$,} k D$D$ D$ DF$R,\1[^_]FVD$FUD$FTD$FSD$H D$ D$ DF$ ,FXD$8 D$ D$ DF$+F\D$p D$ D$ DF$+FdD$F`D$ D$ D$ DF$+FhD$ D$ % D$ DFT$$e+FlD$ D$ D$ DF$@+ D$ D$ D$ D$ D$ D$ DF$* D$ D$ D$ D$,D$ D$ DF$* D$ D$ D$ D$D$ D$ DF$q* D$ D$ D$ D$D$ D$ DF$,* D$XD$ D$ Ё D$ȁ D$DFT$L$ $) D$xD$ D$ DF$)}F8D$D$ % D$ DFT$$s) D$HD$ D$ DF$F)DFD$ D$ $D$ <*DFD$ D$ $D$ *DFD$ D$ $D$ )DFD$ D$ $D$ )KDFD$ D$ $D$ )DFD$ D$ $hD$ j)FZD$dD$ D$ DF$ ( D$D$ D$ DF$''UVS u F=Uf DFD$ D$ $ D$ (DFD$ D$ $ D$ (F t=11fD3D$DFVD$ D$ T$ $H'9^ w1 [^]ÉD$ @FD$UfD$D$ $'UWV1S1ہ } D$ D$ $'DFD$ D$ $ D$ 'DFD$ D$ $ D$ 't& ;_s\D \$ D$ D$ ED$DF$T&9uáDF$ D$|';_rDF$ D$b' 1[^_]ÐUVS˃ D$D$ $ &$N ('D$8"$ D$%FD$d"$ D$%FD$ F D$"$ D$%FD$"$ D$%FD$"$ D$i%F4D$#$ D$N%F&D$@#$ D$2%F(D$ F,D$l#$ D$%tTF D$ FD$#$ D$$F D$ FD$#$ D$$ [^]Ðt& F D$F D$ FD$#$ D$$ [^]Í ' USÃ$ %$L %D$ $$ D$<$CD$8$$ D$!$CD$d$$ D$$C D$$$ D$#CD$$$ D$#CD$$$ D$#[]Í& UVS1ۃD$D$ $ #1D$ $ D$ -D$Y# uЃ[^]Ív UVSӃB(u D$D$% $ #[^]ÉD$D$ $ "$N #$D$%$ D$"CD$@%$ D$"CD$l%$ D$"C D$%$ D$">RtXC D$t&$ D$h"C$D$&$ D$M"C(D$&$ D$2"[^]ËCD$%$ D$"CD$%$ D$!CD$ &$ D$!C D$H&$ D$!7fUSӃ$"CD$5 $ D$ D$!C D$&$ D$ CD$b![]Ít& USӃD$D$ $ 7!$N ["D$@%$ D$!CD$l%$ D$ CD$%$ D$ C D$t&$ D$ CD$&$ D$ CD$&$ D$ C D$ '$ D$l [P ]v UVS D$D$T $ 1 D$ D$h $ D$ 3D$ D$h $ D$ t)uFD$ D$h $ D$ [^]Ív ' UWVS1ۃ $o Dt& \$D$ $ p ;D$!$ D$T tHރt;D$!$ D$& u͡DF$ D$y uDF$ D$\ [^_]Í UVS D$D$ $ DD$ $ T$ D$ u$ [^]Í& USӃD$D$ $ G D$H'$ D$, CD$p'$ D$ CD$'$ D$ C D$'$ D$ CD$'$ D$ CD$($ D$ CD$8($ D$ S ([ ]t& ' UVS$ r $N f $ D$`($ T$ D$ D$($ T$ D$ D$($ D$ D$($ ÉD$g vD \ & e D$ $ dt& & & & uD$ $ D$ $ t& D$* $ D$ D$)$ D$w[^]D$ $ \f D$ $ ;끐D$ $ $g& D$ $ GD$ $ .D$ $ D$ $ UVSӃ u D$D$% $ [^]ÉD$D$ $ `$N C D$ C$D$0)$ D$2C(D$ C,D$X)$ D$C0D$)$ D$C4D$#$ D$C8D$)$ D$$ D$&$ D$CD$)$ D$~CD$ C D$ *$ D$\CD$"$ D$ACD$"$ D$&u:C D$C D$ CD$#$ D$ [^]Í& C D$ CD$(*$ D$C D$ CD$#$ D$ [^]ÐUWVS u ^ $5 $J C`D$L*$ D$DChD$x*$ D$)ClD$*$ D$* ǃ: $^ D$T+$ D$ D$+$ D$ D$+$ D$ D$ D$+$ D$c D$,$ D$DX D$x,$ D$ $w A D$,$ D$ D$,$ D$ D$,$ D$ D$-$ D$ D$8-$ D$v D$\-$ D$( D$-$ D$ D$-$ D$ ( sL #L ~1ɸ 1ɸ Z * t` 9 M g 8 V F 1[^_] D$H,$ D$CdD$*$ D$CtD$*$ D$CpD$(+$ D$opfUWVS u ^ & $5 a$J RC`D$L*$ D$ChD$x*$ D$ClD$*$ D$ ؍ ( dڸ H< L | 1ɸ 1ɸ ڸ { & 1ɸ 1ɸ! 9 R M B g 2 ! 0! D! 1[^_]ËCdD$*$ D$%CtD$*$ D$ CpD$(+$ D$!UWVS ] C{ D$.D$D$ .D$0.$ D$ st01ۍt& DD$ ߃D$ .$ D$r9uփ 1[^_]ÐUVS] DFD$ D$ $X. D$ C D$1D$ D$ DF$CD$1D$ D$ DF$CD$1D$ D$ DF$CD$ 2D$ D$ DF$bC D$D2D$ D$ DF$>C D$h2D$ D$ DF$C$D$2D$ D$ DF$C(D$2D$ D$ DF$C,D$2D$ D$ DF$C0D$2D$ D$ DF$C4D$ 3D$ D$ DF$fC8D$@3D$ D$ DF$BC<D$d3D$ D$ DF$ C@D$3D$ D$ DF$CDD$3D$ D$ DF$CHD$3D$ D$ DF$CLD$3D$ D$ DF$CPD$4D$ D$ DF$jCTD$<4D$ D$ DF$FCXD$`4D$ D$ DF$"C\D$4D$ D$ DF$ C`D$4D$ D$ DF$ CdD$4D$ D$ DF$ ChD$4D$ D$ DF$ ClD$5D$ D$ DF$n CpD$85D$ D$ DF$J DF$ D$DFD$ D$ $D$ 0CtD$k.D$ D$ DF$ CxD$.D$ D$ DF$ C|D$.D$ D$ DF$ D$.D$ D$ DF$} D$.D$ D$ DF$V D$.D$ D$ DF$/ D$/D$ D$ DF$ D$//D$ D$ DF$ D$K/D$ D$ DF$ D$g/D$ D$ DF$ D$/D$ D$ DF$l D$/D$ D$ DF$E DF$ D$ DFD$ D$ $/D$ + D$\5D$ D$ DF$ D$5D$ D$ DF$ D$5D$ D$ DF$ D$5D$ D$ DF$o D$5D$ D$ DF$H D$46D$ D$ DF$! D$t6D$ D$ DF$ D$/D$ D$ DF$ D$/D$ D$ DF$ D$0D$ D$ DF$ D$ 0D$ D$ DF$^ D$;0D$ D$ DF$7 D$X0D$ D$ DF$ D$u0D$ D$ DF$ D$0D$ D$ DF$ D$0D$ D$ DF$ D$6D$ D$ DF$t D$6D$ D$ DF$M D$7D$ D$ DF$& D$0D$ D$ DF$ D$0D$ D$ DF$ D$1D$ D$ DF$ D$"1D$ D$ DF$ D$?1D$ D$ DF$c D$\1D$ D$ DF$< D$y1D$ D$ DF$ D$1D$ D$ DF$ D$(7D$ D$ DF$ D$X7D$ D$ DF$ D$7D$ D$ DF$y D$7D$ D$ DF$RFD$7D$ D$ DF$.DF$ D$i1[^]ÐU]Ít& ' UWVS^ w E )E}Ut+1ƍ ED$E D$E$9}u߃ [^_]Ë $ÐUS @ @t Ћu[]US [l Y[ %s unmodified, ignoring ethtool version 6 -h DEVNAME ethtool %s|%s %s %s %s off Settings for %s: Supported ports: [ AUI BNC MII FIBRE ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full 2500baseX/Full 10000baseT/Full Supports auto-negotiation: Yes No Advertised link modes: Not reported Speed: Unknown! %uMb/s Duplex: Half Full Unknown! (%i) Port: Twisted Pair AUI BNC MII FIBRE PHYAD: %d Transceiver: internal external Auto-negotiation: %s Cannot get device settings Supports Wake-on: %s Wake-on: %s SecureOn password: %s%02x Cannot get message level yes no Link detected: %s Cannot get link status No data available Cannot get driver information Cannot get register dump Can't open '%s': %s Offset Values -------- ----- %03x: %02x Cannot dump registers Cannot test Cannot get strings PASS FAIL The test result is %s The test extra info: %s %d Cannot get control socket Cannot set new settings not setting speed not setting duplex not setting port not setting autoneg not setting phy_address not setting transceiver not setting wol not setting sopass Cannot set new msglvl Cannot get EEPROM data natsemi tg3 Offset Values ------ ------ 0x%04x %02x Cannot set EEPROM data Cannot identify NIC Pause parameters for %s: Coalesce parameters for %s: Adaptive RX: %s TX: %s Ring parameters for %s: Offload parameters for %s: no offload info available no offload settings changed no stats available no memory available Cannot get stats information NIC statistics: %.*s: %llu online offline 2500 10000 duplex half full tp aui bnc mii fibre autoneg advertise phyad xcvr internal external wol sopass %2x:%2x:%2x:%2x:%2x:%2x -s --change Change generic options -a --show-pause Show pause options -A --pause Set pause options -c --show-coalesce Show coalesce options -C --coalesce Set coalesce options -g --show-ring Query RX/TX ring parameters --set-ring Set RX/TX ring parameters -k --show-offload --offload Set protocol offload -i --driver Show driver information -d --register-dump Do a register dump -e --eeprom-dump Do a EEPROM dump -E --change-eeprom Change bytes in device EEPROM -r --negotiate Restart N-WAY negotation -p --identify -t --test Execute adapter self test -S --statistics Show adapter statistics --help Show this help raw hex file offset length magic value rx-mini rx-jumbo adaptive-rx adaptive-tx sample-interval stats-block-usecs pkt-rate-low pkt-rate-high rx-usecs rx-frames rx-usecs-irq rx-frames-irq tx-usecs tx-frames tx-usecs-irq tx-frames-irq rx-usecs-low rx-frames-low tx-usecs-low tx-frames-low rx-usecs-high rx-frames-high tx-usecs-high tx-frames-high sg tso ufo gso gro 8139cp 8139too r8169 de2104x e1000 ixgb e100 amd8111e pcnet32 fec_8xx ibm_emac skge sky2 vioc smsc911x Usage: ethtool DEVNAME Display standard information about device Advertised auto-negotiation: Cannot get wake-on-lan settings Current message level: 0x%08x (%d) Cannot allocate memory for register dump Cannot allocate memory for test info Cannot allocate memory for strings driver: %s version: %s firmware-version: %s bus-info: %s Cannot get current device settings Cannot get current wake-on-lan settings Cannot set new wake-on-lan settings Cannot restart autonegotiation Cannot allocate memory for EEPROM data Autonegotiate: %s RX: %s TX: %s Cannot get device pause settings no pause parameters changed, aborting Cannot set device pause parameters stats-block-usecs: %u sample-interval: %u pkt-rate-low: %u pkt-rate-high: %u rx-usecs: %u rx-frames: %u rx-usecs-irq: %u rx-frames-irq: %u tx-usecs: %u tx-frames: %u tx-usecs-irq: %u tx-frames-irq: %u rx-usecs-low: %u rx-frame-low: %u tx-usecs-low: %u tx-frame-low: %u rx-usecs-high: %u rx-frame-high: %u tx-usecs-high: %u tx-frame-high: %u Cannot get device coalesce settings no ring parameters changed, aborting Cannot set device ring parameters Pre-set maximums: RX: %u RX Mini: %u RX Jumbo: %u TX: %u Current hardware settings: RX: %u RX Mini: %u RX Jumbo: %u TX: %u Cannot get device ring settings Cannot get device rx csum settings Cannot get device tx csum settings Cannot get device scatter-gather settings Cannot get device tcp segmentation offload settings Cannot get device udp large send offload settings Cannot get device generic segmentation offload settings Cannot get device GRO settings rx-checksumming: %s tx-checksumming: %s scatter-gather: %s tcp segmentation offload: %s udp fragmentation offload: %s generic segmentation offload: %s generic-receive-offload: %s Cannot set device rx csum settings Cannot set device tx csum settings Cannot set device scatter-gather settings Cannot set device tcp segmentation offload settings Cannot set device udp large send offload settings Cannot set device generic segmentation offload settings Cannot set device GRO settings Cannot get stats strings information [ speed 10|100|1000|2500|10000 ] [ duplex half|full ] [ port tp|aui|bnc|mii|fibre ] [ autoneg on|off ] [ advertise %%x ] [ phyad %%d ] [ xcvr internal|external ] [ wol p|u|m|b|a|g|s|d... ] [ sopass %%x:%%x:%%x:%%x:%%x:%%x ] [ msglvl %%d ] [ autoneg on|off ] [ rx on|off ] [ tx on|off ] [adaptive-rx on|off] [adaptive-tx on|off] [rx-usecs N] [rx-frames N] [rx-usecs-irq N] [rx-frames-irq N] [tx-usecs N] [tx-frames N] [tx-usecs-irq N] [tx-frames-irq N] [stats-block-usecs N] [pkt-rate-low N] [rx-usecs-low N] [rx-frames-low N] [tx-usecs-low N] [tx-frames-low N] [pkt-rate-high N] [rx-usecs-high N] [rx-frames-high N] [tx-usecs-high N] [tx-frames-high N] [sample-interval N] [ rx N ] [ rx-mini N ] [ rx-jumbo N ] [ tx N ] Get protocol offload information [ rx on|off ] [ tx on|off ] [ sg on|off ] [ tso on|off ] [ ufo on|off ] [ gso on|off ] [ gro on|off ] [ raw on|off ] [ file FILENAME ] [ raw on|off ] [ offset N ] [ length N ] [ magic N ] [ offset N ] [ value N ] Show visible port identification (e.g. blinking) [ TIME-IN-SECONDS ] [ online | offline ] Gqɜv ̉ω ؉ /2 B X[ fė{~ tˊΊ ݊ Й # 3HFI Wphk { ċ ̚ ϋҋ ً$ " `P`P`P ōʍ Ӎ<ۍ `s`ovvDescriptor Registers Command Registers Stopped Enabled Disabled Yes No Interrupt Registers Link status Register 10Mbits/ Sec 100Mbits/Sec Half Valid Invalid 0x00100: Transmit descriptor base address register %08X 0x00140: Transmit descriptor length register 0x%08X 0x00120: Receive descriptor base address register %08X 0x00150: Receive descriptor length register 0x%08X 0x00048: Command 0 register 0x%08X Interrupts: %s Device: %s 0x00050: Command 2 register 0x%08X Promiscuous mode: %s Retransmit on underflow: %s 0x00054: Command 3 register 0x%08X Jumbo frame: %s Admit only VLAN frame: %s Delete VLAN tag: %s 0x00064: Command 7 register 0x%08X 0x00038: Interrupt register 0x%08X Any interrupt is set: %s Link change interrupt: %s Register 0 auto-poll interrupt: %s Transmit interrupt: %s Software timer interrupt: %s Receive interrupt: %s 0x00040: Interrupt enable register 0x%08X Link change interrupt: %s Register 0 auto-poll interrupt: %s Transmit interrupt: %s Software timer interrupt: %s Receive interrupt: %s Logical Address Filter Register 0x00168: Logical address filter register 0x%08X%08X 0x00030: Link status register 0x%08X Link status: %s Auto negotiation complete %s Duplex %s Speed %s 0x00030: Link status register 0x%08X Link status: %s 0x40: CSR8 (Missed Frames Counter) 0x%08x 0x18: CSR3 (Rx Ring Base Address) 0x%08x 0x20: CSR4 (Tx Ring Base Address) 0x%08x 0x00: CSR0 (Bus Mode) 0x%08x %s %s address space Cache alignment: %s Programmable burst length unlimited Programmable burst length %d longwords %s endian data buffers Descriptor skip length %d longwords %s bus arbitration scheme Software reset asserted 0x28: CSR5 (Status) 0x%08x %s Transmit process %s Receive process %s Link %s Normal interrupts: %s%s%s Abnormal intr: %s%s%s%s%s%s%s%s Start/Stop Backoff Counter Flaky oscillator disable 0x30: CSR6 (Operating Mode) 0x%08x %s%s Transmit threshold %d bytes Transmit DMA %sabled %s Operating mode: %s %s duplex %s%s%s%s%s%s%s Receive DMA %sabled %s filtering mode Transmit buffer unavailable Transmit jabber timeout Receive buffer unavailable Receive watchdog timeout Abnormal interrupt summary Normal interrupt summary 0x38: CSR7 (Interrupt Mask) 0x%08x %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s 0x48: CSR9 (Ethernet Address ROM) 0x%08x 0x58: CSR11 (Full Duplex Autoconfig) 0x%08x Network connection error 0x60: CSR12 (SIA Status) 0x%08x %s%s%s%s%s%s%s AUI_TP pin: %s AUI_TP pin autoconfiguration SIA PLL external input enable Encoder input multiplexer Serial interface input multiplexer 0x68: CSR13 (SIA Connectivity) 0x%08x %s%s%s%s External port output multiplexer select: %u%u%u%u %s%s%s%s %s interface selected %s%s%s Collision squelch enable Collision detect enable 0x70: CSR14 (SIA Transmit and Receive) 0x%08x %s%s%s%s%s%s%s %s %s%s%s%s Receive watchdog disable Receive watchdog release 0x78: CSR15 (SIA General) 0x%08x %s%s%s%s%s%s%s%s%s%s 0x00: CSR0 (Bus Mode) 0x%08x %s endian descriptors %s %s address space Cache alignment: %s Normal interrupts: %s%s%s%s%s Abnormal intr: %s%s%s%s%s%s%s Special capture effect enabled Early receive interrupt 0x38: CSR7 (Interrupt Mask) 0x%08x %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s 0x48: CSR9 (Boot and Ethernet ROMs) 0x%08x Select bits: %s%s%s%s%s%s Data: %d%d%d%d%d%d%d%d 0x50: CSR10 (Boot ROM Address) 0x%08x 0x58: CSR11 (General Purpose Timer) 0x%08x %s Timer value: %u cycles Selected port receive activity Non-selected port receive activity Link partner negotiable 0x60: CSR12 (SIA Status) 0x%08x Link partner code word 0x%04x %s NWay state: %s %s%s%s%s%s%s%s%s%s%s%s SIA register reset asserted CSR autoconfiguration enabled 0x68: CSR13 (SIA Connectivity) 0x%08x SIA Diagnostic Mode 0x%04x %s %s%s 10base-T/AUI autosensing 0x70: CSR14 (SIA Transmit and Receive) 0x%08x %s%s%s%s%s%s%s%s%s%s %s %s%s%s%s 0x78: CSR15 (SIA General) 0x%08x %s%s%s%s%s%s%s%s%s%s%s%s %s port selected %s%s%s 16-longword boundary alignment 32-longword boundary alignment Transmit automatic polling every 200 seconds Transmit automatic polling every 800 seconds Transmit automatic polling every 1.6 milliseconds Bus error: (unknown code, reserved) Counter overflow No missed frames %u missed frames 21040 Registers Diagnostic Standard Round-robin RX-has-priority Big Little fail RxOK TxNoBufs TxOK FD_Short AUI_TP RxTimeout RxStopped RxNoBufs TxUnder TxJabber TxStop Hash Perfect en dis Hash-only Filtering Pass Bad Frames Inverse Filtering Promisc Mode Pass All Multicast Forcing collisions Back pressure enabled Capture effect enabled Transmit interrupt Transmit stopped Transmit underflow Receive interrupt Receive stopped AUI_TP pin Full duplex Link fail System error AUI TP Autopolarity state PLL self-test done PLL self-test pass PLL sampler low PLL sampler high SIA reset CSR autoconfiguration 10base-T APLL start Input enable Enable pins 1, 3 Enable pins 2, 4 Enable pins 5, 6, 7 Encoder enable Loopback enable Driver enable Link pulse send enable Receive squelch enable Heartbeat enable Link test enable Autopolarity enable Set polarity plus Jabber disable Host unjab Jabber clock Test clock Force unsquelch Force link fail PLL self-test start Force receiver low 21041 Registers EarlyRx TimerExp ANC Link pass Timer expired ExtReg SROM BootROM Read Mode Continuous mode Unstable NLP detected Transmit remote fault AUI/BNC port 10base-T port Must Be One Autonegotiation enable BNC GP LED1 enable GP LED1 on LED stretch disable GP LED2 enable GP LED2 on not used 8-longword boundary alignment No transmit automatic polling stopped running: fetch desc running: chk pkt end running: wait for pkt suspended running: close running: flush running: queue running: wait xmit end running: read buf unknown (reserved) running: setup packet running: close desc Bus error: parity Bus error: master abort Bus error: target abort normal internal loopback external loopback unknown (not used) Compensation Disabled Mode High Power Mode Normal Compensation Mode Autonegotiation disable Transmit disable Ability detect Acknowledge detect Complete acknowledge FLP link good, nway complete Link check 2;TtYİwȸw 1G[s(((((ȹڹH ` 1IZi| SCB Status Word (Lower Word) 0x%04X RU Status: Idle RU Status: Suspended RU Status: No Resources RU Status: Ready RU Status: Suspended with no more RBDs RU Status: No Resources due to no more RBDs RU Status: Ready with no RBDs present RU Status: Unknown State CU Status: Idle CU Status: Suspended CU Status: Active CU Status: Unknown State ---- Interrupts Pending ---- Flow Control Pause: %s Early Receive: %s Software Generated Interrupt: %s MDI Done: %s RU Not In Ready State: %s CU Not in Active State: %s RU Received Frame: %s CU Completed Command: %s SCB Command Word (Upper Word) 0x%04X RU Command: No Command RU Command: RU Start RU Command: RU Resume RU Command: RU Abort RU Command: Load RU Base RU Command: Unknown CU Command: No Command CU Command: CU Start CU Command: CU Resume CU Command: Load Dump Counters Address CU Command: Dump Counters CU Command: Load CU Base CU Command: Dump & Reset Counters CU Command: Unknown Software Generated Interrupt: %s ---- Interrupts Masked ---- ALL Interrupts: %s Flow Control Pause: %s Early Receive: %s RU Not In Ready State: %s CU Not in Active State: %s RU Received Frame: %s CU Completed Command: %s MDI/MDI-X Status: MDI MDI-X Unknown t >hpF@BlMAC Registers enabled disabled reset big little 10Mb/s 100Mb/s 1000Mb/s no link config PCI Express 64-bit 32-bit 100MHz 66MHz 133MHz PCI-X don't pass ignored filtered accept ignore 1/2 1/4 1/8 reserved 16384 8192 4096 2048 1024 512 256 M88 IGP IGP2 unknown PCI 0x00000: CTRL (Device control register) 0x%08X Endian mode (buffers): %s Link reset: %s Set link up: %s Invert Loss-Of-Signal: %s Receive flow control: %s Transmit flow control: %s VLAN mode: %s Auto speed detect: %s Speed select: %s Force speed: %s Force duplex: %s 0x00008: STATUS (Device status register) 0x%08X Duplex: %s Link up: %s TBI mode: %s Link speed: %s Bus type: %s Port number: %s TBI mode: %s Link speed: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Long packet: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Canonical form indicator: %s Discard pause frames: %s Pass MAC control frames: %s Receive buffer size: %s 0x02808: RDLEN (Receive desc length) 0x%08X 0x02810: RDH (Receive desc head) 0x%08X 0x02818: RDT (Receive desc tail) 0x%08X 0x02820: RDTR (Receive delay timer) 0x%08X 0x00400: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s Pad short packets: %s Software XOFF Transmission: %s Re-transmit on late collision: %s 0x03808: TDLEN (Transmit desc length) 0x%08X 0x03810: TDH (Transmit desc head) 0x%08X 0x03818: TDT (Transmit desc tail) 0x%08X 0x03820: TIDV (Transmit delay timer) 0x%08X PHY type: %s U E E E E 5 5 & & & e e e e u u e u e addr_low 0x%04lx: %-16s 0x%08x addr_high hash_table_high hash_table_low r_des_start x_des_start r_buff_size ecntrl ievent imask ivec r_des_active x_des_active mii_data mii_speed r_bound r_fstart x_fstart fun_code r_cntrl r_hash x_cntrl MAL%d Registers TX| CTP%d = 0x%08x RX| RCBS%d = 0x%08x (%d) EMAC%d Registers IPCR = 0x%08x ZMII%d Registers RGMII%d Registers FER = %08x SSR = %08x TAH%d Registers CFG = 0x%08x ESR = 0x%08x IER = 0x%08x TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x MR0 = 0x%08x MR1 = 0x%08x RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x TRTR = 0x%08x RWMR = 0x%08x IAR = %04x%08x LSA = %04x%08x IAHT = 0x%04x 0x%04x 0x%04x 0x%04x GAHT = 0x%04x 0x%04x 0x%04x 0x%04x VTPID = 0x%04x VTCI = 0x%04x IPGVR = 0x%04x STACR = 0x%08x OCTX = 0x%08x OCRX = 0x%08x FER = %08x SSR = %08x SMIISR = %08x REVID = %08x MR = %08x TSR = %08x SSR0 = %08x SSR1 = %08x SSR2 = %08x SSR3 = %08x SSR4 = %08x SSR5 = %08x 0x00000: CTRL0 (Device control register) 0x%08X Link reset: %s VLAN mode: %s 0x00010: STATUS (Device status register) 0x%08X Link up: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Cononical form indicator: %s 0x00120: RDLEN (Receive desc length) 0x%08X 0x00128: RDH (Receive desc head) 0x%08X 0x00130: RDT (Receive desc tail) 0x%08X 0x00138: RDTR (Receive delay timer) 0x%08X 0x00600: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s 0x00610: TDLEN (Transmit desc length) 0x%08X 0x00618: TDH (Transmit desc head) 0x%08X 0x00620: TDT (Transmit desc tail) 0x%08X 0x00628: TIDV (Transmit delay timer) 0x%08X %s Interrupt: %s Address Data ------- ------ 0x%02x 0x%04x Mac/BIU Registers Active Reset In Progress Up Down Reversed Normal Not Done Not Half/Full 10/100 Advertise In Progress Failed Passed Rx Complete Rx Descriptor Rx Packet Error Rx Early Threshold Rx Idle Rx Overrun Tx Packet OK Tx Descriptor Tx Packet Error Tx Idle Tx Underrun MIB Service Software Power Management Event Phy High Bits Error Rx Status FIFO Overrun Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Rx Reset Complete Tx Reset Complete No Interrupts Active Masked Interrupts %s Accepted Rejected Wake on Arp Enabled SecureOn Hack Detected Phy Interrupt Received Arp Received Pattern 0 Received Pattern 1 Received Pattern 2 Received Pattern 3 Received Magic Packet Received Counters Frozen Value = %d Internal Phy Registers ---------------------- Port Isolated Loopback Enabled Remote Fault Detected Advertising 100Base-T4 Advertising Pause Next Page Desired Supports 100Base-T4 Supports Pause Indicates Remote Fault Reverse MII Interrupt Detected False Carrier Detected Rx Error Detected MII Interrupts %s MII Interrupt Pending Bypassed Free-Running Phase-Adjusted Forced Enhanced Reduced Failed or Not Run 'Magic' Phy Registers Force Detected Magic number 0x%08x does not match 0x%08x 0x00: CR (Command): 0x%08x Transmit %s Receive %s 0x04: CFG (Configuration): 0x%08x %s Endian Boot ROM %s Internal Phy %s Phy Reset %s External Phy %s Default Auto-Negotiation %s, %s %s Mb %s Duplex Phy Interrupt %sAuto-Cleared Phy Configuration = 0x%02x Auto-Negotiation %s %s Polarity %s Duplex %d Mb/s Link %s 0x08: MEAR (EEPROM Access): 0x%08x 0x0c: PTSCR (PCI Test Control): 0x%08x EEPROM Self Test %s Rx Filter Self Test %s Tx FIFO Self Test %s Rx FIFO Self Test %s EEPROM Reload In Progress 0x10: ISR (Interrupt Status): 0x%08x 0x14: IMR (Interrupt Mask): 0x%08x 0x18: IER (Interrupt Enable): 0x%08x 0x20: TXDP (Tx Descriptor Pointer): 0x%08x 0x24: TXCFG (Tx Config): 0x%08x Drain Threshhold = %d bytes (%d) Fill Threshhold = %d bytes (%d) Max DMA Burst per Tx = %d bytes Automatic Tx Padding %s Mac Loopback %s Heartbeat Ignore %s Carrier Sense Ignore %s 0x30: RXDP (Rx Descriptor Pointer): 0x%08x 0x34: RXCFG (Rx Config): 0x%08x Drain Threshhold = %d bytes (%d) Max DMA Burst per Rx = %d bytes Long Packets %s Tx Packets %s Runt Packets %s Error Packets %s 0x3c: CCSR (CLKRUN Control/Status): 0x%08x CLKRUNN %s Power Management %s Power Management Event Pending 0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x Wake on Phy Interrupt Enabled Wake on Unicast Packet Enabled Wake on Multicast Packet Enabled Wake on Broadcast Packet Enabled Wake on Pattern 0 Match Enabled Wake on Pattern 1 Match Enabled Wake on Pattern 2 Match Enabled Wake on Pattern 3 Match Enabled Wake on Magic Packet Enabled Magic Packet SecureOn Enabled Unicast Packet Received Multicast Packet Received Broadcast Packet Received 0x44: PCR (Pause Control/Status): 0x%08x Pause Counter = %d Pause %sNegotiated Pause on DA %s Pause on Mulitcast %s Pause %s PS_RCVD: Pause Frame Received 0x48: RFCR (Rx Filter Control): 0x%08x Unicast Hash %s Multicast Hash %s Arp %s Pattern 0 Match %s Pattern 1 Match %s Pattern 2 Match %s Pattern 3 Match %s Perfect Match %s All Unicast %s All Multicast %s All Broadcast %s Rx Filter %s 0x4c: RFDR (Rx Filter Data): 0x%08x PMATCH 1-0 = 0x%08x PMATCH 3-2 = 0x%08x PMATCH 5-4 = 0x%08x PCOUNT 1-0 = 0x%08x PCOUNT 3-2 = 0x%08x SOPASS 1-0 = 0x%08x SOPASS 3-2 = 0x%08x SOPASS 5-4 = 0x%08x 0x50: BRAR (Boot ROM Address): 0x%08x Automatically Increment Address 0x54: BRDR (Boot ROM Data): 0x%08x 0x58: SRR (Silicon Revision): 0x%08x 0x5c: MIBC (Mgmt Info Base Control): 0x%08x Counter Overflow Warning 0x60: MIB[0] (Rx Errored Packets): 0x%04x 0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x 0x68: MIB[2] (Rx Missed Packets): 0x%02x 0x6c: MIB[3] (Rx Alignment Errors): 0x%02x 0x70: MIB[4] (Rx Symbol Errors): 0x%02x 0x74: MIB[5] (Rx Long Frame Errors): 0x%02x 0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x 0x80: BMCR (Basic Mode Control): 0x%04x %s Duplex Port is Powered %s Auto-Negotiation %s %d Mb/s Auto-Negotiation Restarting 0x84: BMSR (Basic Mode Status): 0x%04x Link %s %sCapable of Auto-Negotiation Auto-Negotiation %sComplete %sCapable of Preamble Suppression %sCapable of 10Base-T Half Duplex %sCapable of 10Base-T Full Duplex %sCapable of 100Base-TX Half Duplex %sCapable of 100Base-TX Full Duplex %sCapable of 100Base-T4 Jabber Condition Detected 0x88: PHYIDR1 (PHY ID #1): 0x%04x 0x8c: PHYIDR2 (PHY ID #2): 0x%04x OUI = 0x%06x Model = 0x%02x (%d) Revision = 0x%01x (%d) 0x90: ANAR (Autoneg Advertising): 0x%04x Protocol Selector = 0x%02x (%d) Advertising 10Base-T Half Duplex Advertising 10Base-T Full Duplex Advertising 100Base-TX Half Duplex Advertising 100Base-TX Full Duplex Indicating Remote Fault 0x94: ANLPAR (Autoneg Partner): 0x%04x Supports 10Base-T Half Duplex Supports 10Base-T Full Duplex Supports 100Base-TX Half Duplex Supports 100Base-TX Full Duplex Indicates Acknowledgement 0x98: ANER (Autoneg Expansion): 0x%04x Link Partner Can %sAuto-Negotiate Link Code Word %sReceived Next Page %sSupported Link Partner Next Page %sSupported Parallel Detection Fault 0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x 0xc0: PHYSTS (Phy Status): 0x%04x Link %s %d Mb/s %s Duplex Auto-Negotiation %sComplete %s Polarity 0xc4: MICR (MII Interrupt Control): 0x%04x 0xc8: MISR (MII Interrupt Status): 0x%04x Rx Error Counter Half-Full Interrupt %s False Carrier Counter Half-Full Interrupt %s Auto-Negotiation Complete Interrupt %s Remote Fault Interrupt %s Jabber Interrupt %s Link Change Interrupt %s 0xcc: PGSEL (Phy Register Page Select): 0x%04x 0xd0: FCSCR (False Carrier Counter): 0x%04x 0xd4: RECR (Rx Error Counter): 0x%04x 0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x NRZI Bypass %s %s Signal Detect Algorithm %s Signal Detect Operation True Quiet Mode %s Rx Clock is %s 4B/5B Operation %s Forced 100 Mb/s Good Link 0xe4: PHYCR (Phy Control): 0x%04x Phy Address = 0x%x (%d) %sPause Compatible with Link Partner LED Stretching %s Phy Self Test %s Self Test Sequence = PSR%d 0xe8: TBTSCR (10Base-T Status/Control): 0x%04x Jabber %s Heartbeat %s Polarity Auto-Sense/Correct %s %s Polarity %s Normal Link Pulse %s 10 Mb/s Loopback %s Forced 10 Mb/s Good Link 0xe4: PMDCSR: 0x%04x 0xf4: DSPCFG: 0x%04x 0xf8: SDCFG: 0x%04x 0xfc: TSTDAT: 0x%04x Driver: %s Version: %s APROM: %04x CSR%02d: BCR%02d: MII%02d: BABL CERR MISS MERR RINT IDON INTR RXON TXON TDMD STOP INIT BABLM MISSM MERRM RINTM TINTM IDONM DXSUFLO LAPPEN DXMT2PD EMBA BSWP EN124 DMAPLUS TXDPOLL APAD_XMT ASTRP_RCV MFCO MFCON UINTCMD UINT RCVCCO RCVCCOM TXSTRT TXSTRTM JAB JABM TOKINTD LTINTEN SINT SINTE SLPINT SLPINTE EXDINT EXDINTE MPPLBA MPINT MPINTE MPEN MPMODE SPND FASTSPNDE RXFRTG RDMD RXDPOLL STINT STINTE MREINT MREINTE MAPINT MAPINTE MCCINT MCCINTE MCCIINT MCCIINTE MIIPDTINT MIIPDTINTE PCnet/PCI 79C970 PCnet/PCI II 79C970A PCnet/FAST 79C971 PCnet/FAST+ 79C972 PCnet/FAST III 79C973 PCnet/Home 79C978 PCnet/FAST III 79C975 PCnet/PRO 79C976 VER: %04x PARTIDU: %04x TMAULOOP LEDPE APROMWE INTLEVEL EADISEL AWAKE ASEL XMAUSEL PVALID EEDET CSR0: Status and Control 0x%04x CSR3: Interrupt Mask 0x%04x CSR4: Test and Features 0x%04x CSR5: Ext Control and Int 1 0x%04x CSR7: Ext Control and Int 2 0x%04x CSR15: Mode 0x%04x CSR40: Current RX Byte Count 0x%04x CSR41: Current RX Status 0x%04x CSR42: Current TX Byte Count 0x%04x CSR43: Current TX Status 0x%04x CSR88: Chip ID Lower 0x%04x CSR89: Chip ID Upper 0x%04x CSR112: Missed Frame Count 0x%04x CSR114: RX Collision Count 0x%04x BCR2: Misc. Configuration 0x%04x BCR9: Full-Duplex Control 0x%04x BCR18: Burst and Bus Control 0x%04x BCR19: EEPROM Control and Status 0x%04x BCR23: PCI Subsystem Vendor ID 0x%04x BCR24: PCI Subsystem ID 0x%04x BCR31: Software Timer 0x%04x BCR32: MII Control and Status 0x%04x BCR35: PCI Vendor ID 0x%04x RxErr TxErr RxNoBuf LinkChg RxFIFO TxNoBuf SWInt TimeOut SERR %s%s%s%s%s%s%s%s%s%s%s unknown RealTek chip ERxOK ERxOverWrite ERxBad ERxGood %s%s%s%s , RESET Big-endian mode Home LAN enable VLAN de-tagging RX checksumming PCI 64-bit DAC PCI Multiple RW RTL-8139 RTL-8139-K RTL-8139A RTL-8139A-G RTL-8139B RTL-8130 RTL-8139C RTL-8100 RTL-8100B/8139D RTL-8139C+ RTL-8101 RTL-8168B/8111B RTL-8101E RTL-8169 RTL-8169s RTL-8110 RealTek %s registers: ------------------------------ 0x00: MAC Address %02x:%02x:%02x:%02x:%02x:%02x 0x08: Multicast Address Filter 0x%08x 0x%08x 0x10: Dump Tally Counter Command 0x%08x 0x%08x 0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x 0x28: Tx High Priority Ring Addr 0x%08x 0x%08x 0x10: Transmit Status Desc 0 0x%08x 0x14: Transmit Status Desc 1 0x%08x 0x18: Transmit Status Desc 2 0x%08x 0x1C: Transmit Status Desc 3 0x%08x 0x20: Transmit Start Addr 0 0x%08x 0x24: Transmit Start Addr 1 0x%08x 0x28: Transmit Start Addr 2 0x%08x 0x2C: Transmit Start Addr 3 0x%08x 0x30: Flash memory read/write 0x%08x 0x30: Rx buffer addr (C mode) 0x%08x 0x34: Early Rx Byte Count %8u 0x36: Early Rx Status 0x%02x 0x37: Command 0x%02x Rx %s, Tx %s%s 0x38: Current Address of Packet Read (C mode) 0x%04x 0x3A: Current Rx buffer address (C mode) 0x%04x 0x3C: Interrupt Mask 0x%04x 0x3E: Interrupt Status 0x%04x 0x40: Tx Configuration 0x%08x 0x44: Rx Configuration 0x%08x 0x48: Timer count 0x%08x 0x4C: Missed packet counter 0x%06x 0x50: EEPROM Command 0x%02x 0x51: Config 0 0x%02x 0x52: Config 1 0x%02x 0x53: Config 2 0x%02x 0x54: Config 3 0x%02x 0x55: Config 4 0x%02x 0x56: Config 5 0x%02x 0x58: Timer interrupt 0x%08x 0x5C: Multiple Interrupt Select 0x%04x 0x60: PHY access 0x%08x 0x64: TBI control and status 0x%08x 0x68: TBI Autonegotiation advertisement (ANAR) 0x%04x 0x6A: TBI Link partner ability (LPAR) 0x%04x 0x6C: PHY status 0x%02x 0x84: PM wakeup frame 0 0x%08x 0x%08x 0x8C: PM wakeup frame 1 0x%08x 0x%08x 0x94: PM wakeup frame 2 (low) 0x%08x 0x%08x 0x9C: PM wakeup frame 2 (high) 0x%08x 0x%08x 0xA4: PM wakeup frame 3 (low) 0x%08x 0x%08x 0xAC: PM wakeup frame 3 (high) 0x%08x 0x%08x 0xB4: PM wakeup frame 4 (low) 0x%08x 0x%08x 0xBC: PM wakeup frame 4 (high) 0x%08x 0x%08x 0xC4: Wakeup frame 0 CRC 0x%04x 0xC6: Wakeup frame 1 CRC 0x%04x 0xC8: Wakeup frame 2 CRC 0x%04x 0xCA: Wakeup frame 3 CRC 0x%04x 0xCC: Wakeup frame 4 CRC 0x%04x 0xDA: RX packet maximum size 0x%04x 0x54: Timer interrupt 0x%08x 0x58: Media status 0x%02x 0x59: Config 3 0x%02x 0x5A: Config 4 0x%02x 0x78: PHY parameter 1 0x%08x 0x7C: Twister parameter 0x%08x 0x80: PHY parameter 2 0x%02x 0x82: Low addr of a Tx Desc w/ Tx DMA OK 0x%04x 0x82: MII register 0x%02x 0x84: PM CRC for wakeup frame 0 0x%02x 0x85: PM CRC for wakeup frame 1 0x%02x 0x86: PM CRC for wakeup frame 2 0x%02x 0x87: PM CRC for wakeup frame 3 0x%02x 0x88: PM CRC for wakeup frame 4 0x%02x 0x89: PM CRC for wakeup frame 5 0x%02x 0x8A: PM CRC for wakeup frame 6 0x%02x 0x8B: PM CRC for wakeup frame 7 0x%02x 0x8C: PM wakeup frame 0 0x%08x 0x%08x 0x94: PM wakeup frame 1 0x%08x 0x%08x 0x9C: PM wakeup frame 2 0x%08x 0x%08x 0xA4: PM wakeup frame 3 0x%08x 0x%08x 0xAC: PM wakeup frame 4 0x%08x 0x%08x 0xB4: PM wakeup frame 5 0x%08x 0x%08x 0xBC: PM wakeup frame 6 0x%08x 0x%08x 0xC4: PM wakeup frame 7 0x%08x 0x%08x 0xCC: PM LSB CRC for wakeup frame 0 0x%02x 0xCD: PM LSB CRC for wakeup frame 1 0x%02x 0xCE: PM LSB CRC for wakeup frame 2 0x%02x 0xCF: PM LSB CRC for wakeup frame 3 0x%02x 0xD0: PM LSB CRC for wakeup frame 4 0x%02x 0xD1: PM LSB CRC for wakeup frame 5 0x%02x 0xD2: PM LSB CRC for wakeup frame 6 0x%02x 0xD3: PM LSB CRC for wakeup frame 7 0x%02x 0xD4: Flash memory read/write 0x%08x 0xD8: Config 5 0x%02x 0xE0: C+ Command 0x%04x 0xE2: Interrupt Mitigation 0x%04x TxTimer: %u TxPackets: %u RxTimer: %u RxPackets: %u 0xE4: Rx Ring Addr 0x%08x 0x%08x 0xEC: Early Tx threshold 0x%02x 0xFC: External MII register 0x%08x 0x5E: PCI revision id 0x%02x 0x60: Transmit Status of All Desc (C mode) 0x%04x 0x62: MII Basic Mode Control Register 0x%04x 0x64: MII Basic Mode Status Register 0x%04x 0x66: MII Autonegotiation Advertising 0x%04x 0x68: MII Link Partner Ability 0x%04x 0x6A: MII Expansion 0x%04x 0x6C: MII Disconnect counter 0x%04x 0x6E: MII False carrier sense counter 0x%04x 0x70: MII Nway test 0x%04x 0x72: MII RX_ER counter 0x%04x 0x74: MII CS configuration 0x%04x Address Data ---------- ---- 0x%08x 0x%02x Offset Value ------ ---------- 0x%04x 0x%08x \ H \" $ $ ( ( , , 0 0 4 4 8 8 < = @ @ D XD H H L L P R T V X Z \ ] ` ` h Hh p 4p | @~ %s Control Registers %-32s 0x%08X %s (disabled) Init 0x%08X Value 0x%08X LED Addr %d %02X%c PCI config ---------- %02x: %12s address: %02X %02X Physical MAC Addresses Genesis Yukon Yukon-Lite Yukon-LP Yukon-2 XL Yukon Extreme Yukon-2 EC Ultra Yukon-2 EC Yukon-2 FE (Unknown) (rev %d) Bus Management Unit ------------------- Status BMU: ----------- Status FIFO Status level TX status ISR Rx GMAC 1 Tx GMAC 1 Receive Queue 1 Sync Transmit Queue 1 Async Transmit Queue 1 Receive RAMbuffer 1 Sync Transmit RAMbuffer 1 Async Transmit RAMbuffer 1 Receive RAMbuffer 2 Sync Transmit RAMbuffer 2 Async Transmit RAMbuffer 21 Rx GMAC 2 Tx GMAC 2 Timer IRQ Moderation Blink Source Receive MAC FIFO 1 Transmit MAC FIFO 1 Receive Queue 2 Async Transmit Queue 2 Sync Transmit Queue 2 Receive MAC FIFO 2 Transmit MAC FIFO 2 Descriptor Poll End Address Almost Full Thresh Control/Test FIFO Flush Mask FIFO Flush Threshold Truncation Threshold Upper Pause Threshold Lower Pause Threshold VLAN Tag FIFO Write Pointer FIFO Write Level FIFO Read Pointer FIFO Read Level Buffer control 0x%04X Byte Counter %d Descriptor Address 0x%08X%08X Status 0x%08X Timestamp 0x%08X BMU Control/Status 0x%08X Done 0x%04X Request 0x%08X%08X Csum1 Offset %4d Position %d Csum2 Offset %4d Position %d Csum Start 0x%04X Pos %4d Write %d Register Access Port 0x%02X LED Control/Status 0x%08X Interrupt Source 0x%08X Interrupt Mask 0x%08X Interrupt Hardware Error Source 0x%08X Interrupt Hardware Error Mask 0x%08X Start Address 0x%08X End Address 0x%08X Write Pointer 0x%08X Read Pointer 0x%08X Upper Threshold/Pause Packets 0x%08X Lower Threshold/Pause Packets 0x%08X Upper Threshold/High Priority 0x%08X Lower Threshold/High Priority 0x%08X Packet Counter 0x%08X Level 0x%08X Control 0x%08X Test 0x%02X Control 0x%02X Control/Test 0x%08X Status 0x%04X Control 0x%04X Transmit 0x%04X Receive 0x%04X Transmit flow control 0x%04X Transmit parameter 0x%04X Serial mode 0x%04X Connector type 0x%02X (%c) PMD type 0x%02X (%c) PHY type 0x%02X Chip Id 0x%02X Ram Buffer 0x%02X Descriptor Address 0x%08X%08X Address Counter 0x%08X%08X Current Byte Counter %d Flag & FIFO Address 0x%08X Next 0x%08X Data 0x%08X%08X Csum1 Offset %4d Position %d CSR Receive Queue 1 0x%08X CSR Sync Queue 1 0x%08X CSR Async Queue 1 0x%08X CSR Receive Queue 2 0x%08X CSR Async Queue 2 0x%08X CSR Sync Queue 2 0x%08X Control 0x%08X Last Index 0x%04X Put Index 0x%04X List Address 0x%08X%08X Transmit 1 done index 0x%04X Transmit 2 done index 0x%04X Transmit index threshold 0x%04X Write Pointer 0x%02X Read Pointer 0x%02X Level 0x%02X Watermark 0x%02X ISR Watermark 0x%02X GMAC control 0x%04X GPHY control 0x%04X LINK control 0x%02hX T!`!s!!!!!!!!""%"version cmd %08x = %08x ethtool_regs %-20s = %04x %-20s = %04x LAN911x Registers index 1, MAC_CR = 0x%08X index 2, ADDRH = 0x%08X index 3, ADDRL = 0x%08X index 4, HASHH = 0x%08X index 5, HASHL = 0x%08X index 6, MII_ACC = 0x%08X index 7, MII_DATA = 0x%08X index 8, FLOW = 0x%08X index 9, VLAN1 = 0x%08X index A, VLAN2 = 0x%08X index B, WUFF = 0x%08X index C, WUCSR = 0x%08X PHY Registers index 7, Reserved = 0x%04X index 8, Reserved = 0x%04X index 9, Reserved = 0x%04X index 10, Reserved = 0x%04X index 11, Reserved = 0x%04X index 12, Reserved = 0x%04X index 13, Reserved = 0x%04X index 14, Reserved = 0x%04X index 15, Reserved = 0x%04X index 19, Reserved = 0x%04X index 20, TSTCNTL = 0x%04X index 21, TSTREAD1 = 0x%04X index 22, TSTREAD2 = 0x%04X index 23, TSTWRITE = 0x%04X index 24, Reserved = 0x%04X index 25, Reserved = 0x%04X index 26, Reserved = 0x%04X offset 0x50, ID_REV = 0x%08X offset 0x54, INT_CFG = 0x%08X offset 0x58, INT_STS = 0x%08X offset 0x5C, INT_EN = 0x%08X offset 0x60, RESERVED = 0x%08X offset 0x64, BYTE_TEST = 0x%08X offset 0x68, FIFO_INT = 0x%08X offset 0x6C, RX_CFG = 0x%08X offset 0x70, TX_CFG = 0x%08X offset 0x74, HW_CFG = 0x%08X offset 0x78, RX_DP_CTRL = 0x%08X offset 0x7C, RX_FIFO_INF = 0x%08X offset 0x80, TX_FIFO_INF = 0x%08X offset 0x84, PMT_CTRL = 0x%08X offset 0x88, GPIO_CFG = 0x%08X offset 0x8C, GPT_CFG = 0x%08X offset 0x90, GPT_CNT = 0x%08X offset 0x94, FPGA_REV = 0x%08X offset 0x98, ENDIAN = 0x%08X offset 0x9C, FREE_RUN = 0x%08X offset 0xA0, RX_DROP = 0x%08X offset 0xA4, MAC_CSR_CMD = 0x%08X offset 0xA8, MAC_CSR_DATA = 0x%08X offset 0xAC, AFC_CFG = 0x%08X offset 0xB0, E2P_CMD = 0x%08X offset 0xB4, E2P_DATA = 0x%08X index 0, Basic Control Reg = 0x%04X index 1, Basic Status Reg = 0x%04X index 2, PHY identifier 1 = 0x%04X index 3, PHY identifier 2 = 0x%04X index 4, Auto Negotiation Advertisement Reg = 0x%04X index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X index 6, Auto Negotiation Expansion Register = 0x%04X index 16, Silicon Revision Reg = 0x%04X index 17, Mode Control/Status Reg = 0x%04X index 18, Special Modes = 0x%04X index 27, Control/Status Indication = 0x%04X index 28, Special internal testability = 0x%04X index 29, Interrupt Source Register = 0x%04X index 30, Interrupt Mask Register = 0x%04X index 31, PHY Special Control/Status Register = 0x%04X ;X * Rp S T U V f j, mP t P 4 T t 0 @P 'p ( ) `+ 0, , ., .H /d 00 1 p1 2 05 @7 p;@ =` > | z AB AG 8 AB F X 0 AB BF x AD ! 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